The present invention relates to a semiconductor failure analysis system and a semiconductor checking apparatus and, particularly relates to a semiconductor failure analyzing system adapted for analysis the cause of a failure in a semiconductor wafer production process and a semiconductor checking apparatus used in the failure analysis system.
According to one conventional semiconductor failure analysis system namely, JP-A-61-243378, a failure analysis system is provided in which: distribution patterns of points obtained by an electrical test and an indication of whether the quality of a subject under inspection is good or bad are classified into basic patterns so that the basic patterns are stored in a storage device; information indicating a plurality of possibilities that a failure has occurred in the subject inspection is generated correspondingly to basic patterns obtained from basic failure information which can be considered with respect to the all basic patterns stored in the storage device; and the coordinates of points at which the occurrence of the failure is estimated are automatically transferred to an observation apparatus.
In the conventional system, there is however no consideration that means for observing information concerned with results of failure analysis systematically from a large number of viewpoints is provided in an user interface of the system. That is, there is no consideration that information concerned with results of failure analysis, such as display indicating fail bits on the whole of a wafer, display indicating the distribution of fail bits on an arbitrary chip, enlarged display indicating the distribution of fail bits in a partial area of a chip, and so on, is used speedily and smoothly. Whether the aforementioned information is to be displayed or not to be displayed, it is necessary to operate a display unit to switch the scene on the display unit to a new scene. Accordingly, operations which can be very troublesome for users are often required.
Further, in the conventional system, there has been proposed no method in which the sizes of memory cells can be confirmed visually with respect to the user interface of the system when information is displayed.
Further, in the conventional semiconductor failure analysis system, no consideration is given that errors may occur when the coordinates of points at which the occurrence of the failure is estimated are transferred to the observation apparatus because different coordinate reference points are used. Further, patterns of generation of fail bits are classified, but there is no specific rule for the classification. In the conventional system, therefore, all causes of failure distributions are estimated so that a small number of basic patterns thus classified have one-to-one correspondence with the causes of the failure. In the conventional system, however no consideration is given that a plurality of causes of the failure correspond to one and the same pattern of fail bits, though such correspondence must be thought of. Further, because the causes related to the basic patterns are difficult to determine, a large time is required for examining the true cause of the failure. Further, because there is no consideration that the relation between the pattern of generation of fail bits and the cause of the failure varies in accordance with the subject under inspection, the conventional system cannot be adapted to multikind subjects of inspection.
Further, because there has not been proposed a function of managing the situation of occurrence of fail bits statistically on the basis of the classified basic patterns to thereby feed results of the management back to a production process, the conventional system has a risk that the occurrence of a failure may be detected later when the failure has occurred in the production process.
In addition, though a micro analyzing method in which the situation of occurrence of fail bits in a wafer or in a chip is analyzed bit by bit is employed in the conventional system, there has not been proposed a macro analyzing method in which the patterns of generation of fail bits are categorized so that macro analysis is performed by using the category thereof.